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Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard.cite-ref-1[1] The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket.cite-ref-2[2]

• ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package.cite-ref-specs-3-0[3]

• There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups:

• Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link.

• GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP).

All PCIe links are capable of supporting PCIe 2.0 data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate.cite-ref-specs-3-1[3]

For available chipsets consult Fusion controller hubs (FCH).

Its mobile counterpart is Socket FP3 (μBGA906).

• Heatsink

• Feature overview

• External links

The 4 holes for fastening the heatsink to the motherboard are placed in a rectangle with lateral lengths of 48 mm and 96 mm for AMD's sockets Socket AM2, Socket AM2+, Socket AM3, Socket AM3+ and Socket FM2. Cooling solutions should therefore be interchangeable.

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

| Platform | Platform | Platform | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

| Codename | Server | Basic | | | | | | Toronto | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Server | Micro | | | | | | | | | | | | | | | | Kyoto | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Desktop | Performance | | | | | | | | | | | | | Raphael | Phoenix | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Desktop | Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | Raphael | Phoenix | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Desktop | Entry | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | | Phoenix | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Desktop | Basic | | | | | | | | | | | | | | | | Kabini | | | | Dalí | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Mobile | Performance | | | | | | | | | | Renoir | Cezanne | Rembrandt | Dragon Range | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Mobile | Mainstream | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne | Cezanne Barceló | Rembrandt | Dragon Range | Phoenix | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Mobile | Entry | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | | | | | | | | | | | | Dalí | | | Mendocino | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Mobile | Basic | | | | | | | | | | | | | | | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Dalí | Pollock | | Mendocino | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Codename | Embedded | Embedded | | Trinity | | Bald Eagle | | Merlin Falcon , Brown Falcon | | Great Horned Owl | | Grey Hawk | | | | | Ontario, Zacate | Kabini | Steppe Eagle , Crowned Eagle , LX-Family | | Prairie Falcon | Banded Kestrel | | River Hawk | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Released | Released | Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| CPU microarchitecture | CPU microarchitecture | CPU microarchitecture | K10 | Piledriver | Piledriver | Steamroller | Steamroller | Excavator | " Excavator+ " [ 4 ] | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Zen 4 | Bobcat | Jaguar | Puma | Puma+ [ 5 ] | " Excavator+ " | Zen | Zen | Zen+ | " Zen 2+ " | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| ISA | ISA | ISA | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v4 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Socket | Desktop | Performance | — | — | — | — | — | — | — | — | — | — | — | — | AM5 | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Socket | Desktop | Mainstream | — | — | — | — | — | AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | AM5 | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Socket | Desktop | Entry | FM1 | FM2 | FM2 | | | [ a ] , AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Socket | Desktop | Basic | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | AM1 | — | — | — | FP5 | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Socket | Other | Other | FS1 | FS1+ , FP2 | FS1+ , FP2 | FP3 | FP3 | FP4 | FP4 | FP5 | FP5 | FP6 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 | FT1 | FT3 | FT3b | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| PCI Express version | PCI Express version | PCI Express version | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| CXL | CXL | CXL | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Fab. ( nm ) | Fab. ( nm ) | Fab. ( nm ) | GF 32SHP ( HKMG SOI ) | GF 32SHP ( HKMG SOI ) | GF 32SHP ( HKMG SOI ) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP ( FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N6 (FinFET bulk) | CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) | TSMC 4nm (FinFET bulk) | TSMC N40 (bulk) | TSMC N28 (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP ( FinFET bulk) | GF 14LPP ( FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N6 (FinFET bulk) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Die area (mm 2 ) | Die area (mm 2 ) | Die area (mm 2 ) | 228 | 246 | 246 | 245 | 245 | 245 | 250 | 210 [ 6 ] | 210 [ 6 ] | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 | 178 | 75 (+ 28 FCH ) | 107 | 107 | ? | 125 | 149 | | | ~100 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Min TDP (W) | Min TDP (W) | Min TDP (W) | 35 | 17 | 17 | 17 | 17 | 12 | 12 | 12 | 12 | 10 | 10 | 15 | 65 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 6 | 6 | 12 | 8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max APU TDP (W) | Max APU TDP (W) | Max APU TDP (W) | 100 | 100 | 100 | 95 | 95 | 65 | 65 | 65 | 65 | 65 | 65 | 45 | 170 | 54 | 18 | 25 | 25 | 25 | 25 | 25 | 6 | 54 | 15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 4.0 | 3.3 | 4.7 | 4.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 2.6 | 1.2 | 3.35 | 2.8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max APUs per node [ b ] | Max APUs per node [ b ] | Max APUs per node [ b ] | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max core dies per CPU | Max core dies per CPU | Max core dies per CPU | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max CCX per core die | Max CCX per core die | Max CCX per core die | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max cores per CCX | Max cores per CCX | Max cores per CCX | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max CPU [ c ] cores per APU | Max CPU [ c ] cores per APU | Max CPU [ c ] cores per APU | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 16 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max threads per CPU core | Max threads per CPU core | Max threads per CPU core | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Integer pipeline structure | Integer pipeline structure | Integer pipeline structure | 3+3 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 4+2 | 4+2 | 4+2+1 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 2+2 | 4+2 | 4+2 | 4+2 | 4+2+1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| i386, i486, i586, CMOV, NOPL, i686, PAE , NX bit , CMPXCHG16B, AMD-V , RVI , ABM , and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE , NX bit , CMPXCHG16B, AMD-V , RVI , ABM , and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE , NX bit , CMPXCHG16B, AMD-V , RVI , ABM , and 64-bit LAHF/SAHF | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| IOMMU [ d ] | IOMMU [ d ] | IOMMU [ d ] | — | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v1 | v1 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| BMI1 , AES-NI , CLMUL , and F16C | BMI1 , AES-NI , CLMUL , and F16C | BMI1 , AES-NI , CLMUL , and F16C | — | | | | | | | | | | | | | | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| MOVBE | MOVBE | MOVBE | — | — | — | — | — | | | | | | | | | | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| AVIC , BMI2 , RDRAND , and MWAITX/MONITORX | AVIC , BMI2 , RDRAND , and MWAITX/MONITORX | AVIC , BMI2 , RDRAND , and MWAITX/MONITORX | — | — | — | — | — | | | | | | | | | | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| SME [ e ] , TSME [ e ] , ADX , SHA , RDSEED , SMAP , SMEP , XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME [ e ] , TSME [ e ] , ADX , SHA , RDSEED , SMAP , SMEP , XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME [ e ] , TSME [ e ] , ADX , SHA , RDSEED , SMAP , SMEP , XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | — | — | — | — | — | — | — | | | | | | | | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| GMET , WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET , WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET , WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | — | — | — | — | — | — | — | — | — | | | | | | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| MPK , VAES | MPK , VAES | MPK , VAES | — | — | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| SGX | SGX | SGX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| FPUs per core | FPUs per core | FPUs per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Pipes per FPU | Pipes per FPU | Pipes per FPU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| FPU pipe width | FPU pipe width | FPU pipe width | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit | 256-bit | 256-bit | 256-bit | 256-bit | 80-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| CPU instruction set SIMD level | CPU instruction set SIMD level | CPU instruction set SIMD level | SSE4a [ f ] | AVX | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX-512 | AVX-512 | SSSE3 | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| 3DNow! | 3DNow! | 3DNow! | 3DNow!+ | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| GFNI | GFNI | GFNI | — | — | — | — | — | — | — | — | — | — | — | — | | | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| AMX | AMX | AMX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| FMA4 , LWP, TBM , and XOP | FMA4 , LWP, TBM , and XOP | FMA4 , LWP, TBM , and XOP | — | | | | | | | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| FMA3 | FMA3 | FMA3 | — | | | | | | | | | | | | | | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| AMD XDNA | AMD XDNA | AMD XDNA | — | — | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L1 data cache per core (KiB) | L1 data cache per core (KiB) | L1 data cache per core (KiB) | 64 | 16 | 16 | 16 | 16 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L1 data cache associativity (ways) | L1 data cache associativity (ways) | L1 data cache associativity (ways) | 2 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L1 instruction caches per core | L1 instruction caches per core | L1 instruction caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | 256 | 128 | 128 | 192 | 192 | 192 | 192 | 256 | 256 | 256 | 256 | 256 | 512 | 256 | 64 | 64 | 128 | 128 | 96 | 128 | 128 | 128 | 128 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | 2 | 2 | 2 | 3 | 3 | 3 | 3 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 2 | 2 | 2 | 2 | 3 | 4 | 4 | 4 | 8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L2 caches per core | L2 caches per core | L2 caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 4 | 4 | 4 | 16 | | 1 | 2 | 2 | 2 | 1 | 1 | 1 | 2 | 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L2 cache associativity (ways) | L2 cache associativity (ways) | L2 cache associativity (ways) | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max on-die L3 cache per CCX (MiB) | Max on-die L3 cache per CCX (MiB) | Max on-die L3 cache per CCX (MiB) | — | — | — | — | — | — | — | 4 | 4 | 4 | 16 | 16 | 32 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 64 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 128 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | — | — | — | — | — | — | — | 16 | 16 | 16 | 16 | 16 | 16 | 16 | — | — | — | — | — | — | 16 | 16 | 16 | 16 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| L3 cache scheme | L3 cache scheme | L3 cache scheme | — | — | — | — | — | — | — | Victim | Victim | Victim | Victim | Victim | Victim | Victim | — | — | — | — | — | — | Victim | Victim | Victim | Victim | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max. L4 cache | Max. L4 cache | Max. L4 cache | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max stock DRAM support | Max stock DRAM support | Max stock DRAM support | DDR3 -1866 | DDR3 -1866 | DDR3-2133 | DDR3-2133 | DDR3-2133 | DDR3-2133, DDR4 -2400 | DDR4-2400 | DDR4-2933 | DDR4-2933 | DDR4-3200, LPDDR4 -4266 | DDR4-3200, LPDDR4 -4266 | DDR5 -4800, LPDDR5 -6400 | DDR5 -5200 | DDR5 -5600, LPDDR5x -7500 | DDR3L -1333 | DDR3L-1600 | DDR3L-1866 | DDR3L-1866 | DDR3-1866, DDR4 -2400 | DDR4-2400 | DDR4-1600 | DDR4-3200 | LPDDR5-5500 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max DRAM channels per APU | Max DRAM channels per APU | Max DRAM channels per APU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 2 | 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 29.866 | 34.132 | 34.132 | 34.132 | 38.400 | 38.400 | 46.932 | 46.932 | 68.256 | 68.256 | 102.400 | 83.200 | 120.000 | 10.666 | 12.800 | 14.933 | 14.933 | 19.200 | 38.400 | 12.800 | 51.200 | 88.000 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| GPU microarchitecture | GPU microarchitecture | GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen | GCN 3rd gen | GCN 5th gen [ 7 ] | GCN 5th gen [ 7 ] | GCN 5th gen [ 7 ] | GCN 5th gen [ 7 ] | RDNA 2 | RDNA 2 | RDNA 3 | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen [ 7 ] | GCN 5th gen | GCN 5th gen | GCN 5th gen | RDNA 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| GPU instruction set | GPU instruction set | GPU instruction set | TeraScale instruction set | TeraScale instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set | RDNA instruction set | RDNA instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 866 | 1108 | 1108 | 1250 | 1400 | 2100 | 2100 | 2400 | 400 | | 538 | 600 | ? | 847 | 900 | 1200 | 600 | 1300 | 1900 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Max stock GPU base GFLOPS [ g ] | Max stock GPU base GFLOPS [ g ] | Max stock GPU base GFLOPS [ g ] | 480 | 614.4 | 648.1 | 886.7 | 886.7 | 1134.5 | 1134.5 | 1760 | 1971.2 | 2150.4 | 2150.4 | 3686.4 | 102.4 | | 86 | ? | ? | ? | 345.6 | 460.8 | 230.4 | 1331.2 | 486.4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| 3D engine [ h ] | 3D engine [ h ] | 3D engine [ h ] | Up to 400:20:8 | Up to 384:24:6 | Up to 384:24:6 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 704:44:16 [ 8 ] | Up to 704:44:16 [ 8 ] | Up to 512:32:8 | Up to 512:32:8 | 768:48:8 | 128:8:4 | | 80:8:4 | 128:8:4 | 128:8:4 | 128:8:4 | Up to 192:12:8 | Up to 192:12:4 | 192:12:4 | Up to 512:?:? | 128:?:? | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| 3D engine [ h ] | 3D engine [ h ] | 3D engine [ h ] | IOMMUv1 | IOMMUv1 | IOMMUv1 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv1 | IOMMUv1 | ? | ? | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Video decoder | Video decoder | Video decoder | UVD 3.0 | UVD 3.0 | UVD 3.0 | UVD 4.2 | UVD 4.2 | UVD 6.0 | UVD 6.0 | VCN 1.0 [ 9 ] | VCN 1.0 [ 9 ] | VCN 2.1 [ 10 ] | VCN 2.2 [ 10 ] | VCN 3.1 | VCN 3.1 | ? | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 4.2 | UVD 6.2 | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Video encoder | Video encoder | Video encoder | — | VCE 1.0 | VCE 1.0 | VCE 2.0 | VCE 2.0 | VCE 3.1 | VCE 3.1 | VCN 1.0 [ 9 ] | VCN 1.0 [ 9 ] | VCN 2.1 [ 10 ] | VCN 2.2 [ 10 ] | VCN 3.1 | VCN 3.1 | ? | — | VCE 2.0 | VCE 2.0 | VCE 2.0 | VCE 3.4 | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| AMD Fluid Motion | AMD Fluid Motion | AMD Fluid Motion | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| GPU power saving | GPU power saving | GPU power saving | PowerPlay | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerPlay | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | PowerTune [ 11 ] | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| TrueAudio | TrueAudio | TrueAudio | — | — | — | [ 12 ] | [ 12 ] | [ 12 ] | [ 12 ] | [ 12 ] | [ 12 ] | [ 12 ] | ? | ? | ? | ? | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| FreeSync | FreeSync | FreeSync | — | — | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 |

| HDCP [ i ] | HDCP [ i ] | HDCP [ i ] | ? | ? | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.2 | 2.3 | 2.3 | 2.3 | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| PlayReady [ i ] | PlayReady [ i ] | PlayReady [ i ] | — | — | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| Supported displays [ j ] | Supported displays [ j ] | Supported displays [ j ] | 2–3 | 2–4 | 2–4 | 2–4 | 2–4 | 3 | 3 | 3 (desktop) 4 (mobile, embedded) | 3 (desktop) 4 (mobile, embedded) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 3 | 4 | | 4 | 4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| /drm/radeon [ k ] [ 14 ] [ 15 ] | /drm/radeon [ k ] [ 14 ] [ 15 ] | /drm/radeon [ k ] [ 14 ] [ 15 ] | | | | | | | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

| /drm/amdgpu [ k ] [ 16 ] | /drm/amdgpu [ k ] [ 16 ] | /drm/amdgpu [ k ] [ 16 ] | — | — | — | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | — | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | [ 17 ] | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |

cite-note-61. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.

cite-note-nodedef-82. A PC would be one node.

cite-note-apudef-93. An APU combines a CPU and a GPU. Both have cores.

cite-note-iommubios-104. Requires firmware support.

cite-note-firmware-115. Requires firmware support.

cite-note-sse4a-126. No SSE4. No SSSE3.

cite-note-sflops-147. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

cite-note-158. Unified shaders : texture mapping units : render output units

cite-note-drm-219. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.

cite-note-2310. To feed more than two displays, the additional panels must have native DisplayPort support.cite-ref-22[13] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.

cite-note-drm-2411. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

cite-note-11. ↑ "AMD Socket FM2 Plus Platform". AMD. Retrieved November 28, 2022.

cite-note-22. ↑ citerefbroekhuijsen2013Broekhuijsen, Niels (June 6, 2013). "Report: Upcoming Socket FM2+ Will Support Older Trinity and Richland APUs". Tom's Hardware. Retrieved November 28, 2022.

cite-note-specs-33. ↑ "BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 30h-3Fh Processors" (PDF). AMD. February 10, 2015. Retrieved November 28, 2022.

cite-note-412. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.

cite-note-513. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.

cite-note-714. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.

cite-note-vega-codenames-1315. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.

cite-note-1616. citerefcutress2018Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.

cite-note-1717. citereflarabel2017Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.

cite-note-wccftechcezanne-1818. "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.

cite-note-1919. citereftony-chenjason-greavesTony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016

cite-note-2020. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.

cite-note-2213. ↑ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.

cite-note-2521. citerefairlie2009Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.

cite-note-radeon-feature-matrix-2622. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.

cite-note-2723. citerefdeucher2015Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.

cite-note-amdgpu-1-2-2824. citerefmichel-d-nzer2016Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.